`timescale 1ns / 1ps
module ps2_connect(
    PS2C,
    PS2D,
    CLK1,
    RST,
	 kb_ascii_out,
	 kb_data_valid
    );

inout PS2C;
inout PS2D;
input CLK1;
input RST;
output [7:0] kb_ascii_out;
output kb_data_valid;


wire [7:0] rx_data;
wire [7:0] tx_data;
wire ps2_write, ps2_read, ps2_busy, ps2_err;

ps2interface ps2inface(
	.ps2_clk(PS2C),
	.ps2_data(PS2D),
	.clk(CLK1),
	.rst(RST),
	.rx_data(rx_data),
	.tx_data(tx_data),
	.write(ps2_write),
	.read(ps2_read),
	.err(ps2_err),
	.busy(ps2_busy)
);

kb2ascii kbass(
	.clk(CLK1),
	.rst(RST),
	.scan_code(rx_data),
	.ascii(kb_ascii_out),
	.ascii_valid(kb_data_valid),
	.kb_read(ps2_read)
);

endmodule
